An 8-channel, 46-ps-precision TDC ASIC with improved vernier delay loop for STCF EMC

摘要: An 8-channel time-to-digital converter (TDC) with high precision and linearity designed for the electromagnetic
calorimeter (EMC) in the Super Tau-charm Facility (STCF) is presented. A 3-level quantization structure
is employed in the proposed TDC to achieve high time resolution and wide dynamic range simultaneously. A
double-edge-triggered counter characterized by the elimination of metastability is used as the first level. The
second and third levels are respectively implemented with a polyphase clock sampler and a modified Vernier
delay loop (VDL) with an automatic reset mechanism. Two low-jitter delay-locked loops (DLLs) with different
lengths are utilized to assist in vernier measurement and polyphase clocks are also provided by one of the DLLs.
A theoretical analysis with respect to the optimal combination of DLL length and reference clock frequency is
presented. The proposed 8-channel TDC was implemented using 180nm standard CMOS process with 1.8V
power supply. Under a reference clock frequency of 100MHz, the TDC is realized with a resolution of 41.7 ps
and a dynamic range of 2560 ns. According to the results of an experimental evaluation, the best single-shot
precision was 46 ps, and good consistency was observed among all channels. The results also establish that the
sliding scale technique improved conversion linearity. In asynchronous measurements, the maximum differential
nonlinearity (DNL) and the integral nonlinearity (INL) were less than 0.4 LSB and 0.5 LSB, respectively.